REG_D 621 libavcodec/x86/snowdsp.c "mov %1, %%"REG_D" \n\t"\ REG_D 622 libavcodec/x86/snowdsp.c "mov (%%"REG_D"), %%"REG_D" \n\t"\ REG_D 623 libavcodec/x86/snowdsp.c "add %3, %%"REG_D" \n\t" REG_D 675 libavcodec/x86/snowdsp.c "%"REG_c"","%"REG_S"","%"REG_D"","%"REG_d""); REG_D 700 libavcodec/x86/snowdsp.c "movdqa (%%"REG_D"), %%xmm0 \n\t" REG_D 706 libavcodec/x86/snowdsp.c "movdqa 16(%%"REG_D"), %%xmm2 \n\t" REG_D 711 libavcodec/x86/snowdsp.c "mov %1, %%"REG_D" \n\t" REG_D 712 libavcodec/x86/snowdsp.c "mov "PTR_SIZE"(%%"REG_D"), %%"REG_D";\n\t" REG_D 713 libavcodec/x86/snowdsp.c "add %3, %%"REG_D" \n\t" REG_D 715 libavcodec/x86/snowdsp.c "movdqa (%%"REG_D"), %%xmm4 \n\t" REG_D 720 libavcodec/x86/snowdsp.c "movdqa 16(%%"REG_D"), %%xmm6 \n\t" REG_D 750 libavcodec/x86/snowdsp.c "paddw (%%"REG_D"), %%xmm1 \n\t" REG_D 751 libavcodec/x86/snowdsp.c "paddw 16(%%"REG_D"), %%xmm5 \n\t" REG_D 775 libavcodec/x86/snowdsp.c "mov %1, %%"REG_D" \n\t"\ REG_D 776 libavcodec/x86/snowdsp.c "mov (%%"REG_D"), %%"REG_D" \n\t"\ REG_D 777 libavcodec/x86/snowdsp.c "add %3, %%"REG_D" \n\t" REG_D 801 libavcodec/x86/snowdsp.c "paddw "read_offset"(%%"REG_D"), %%mm1 \n\t"\ REG_D 802 libavcodec/x86/snowdsp.c "paddw "read_offset"+8(%%"REG_D"), %%mm5 \n\t"\ REG_D 823 libavcodec/x86/snowdsp.c "%"REG_c"","%"REG_S"","%"REG_D"","%"REG_d""); REG_D 73 libswscale/x86/hscale_fast_bilinear_simd.c "movq %%mm0, (%%"REG_D", %%"REG_a") \n\t" REG_D 111 libswscale/x86/hscale_fast_bilinear_simd.c "movq %%mm0, (%%"REG_D", %%"REG_a") \n\t" REG_D 223 libswscale/x86/hscale_fast_bilinear_simd.c "mov %1, %%"REG_D" \n\t" REG_D 237 libswscale/x86/hscale_fast_bilinear_simd.c "add %%"REG_a", %%"REG_D" \n\t"\ REG_D 245 libswscale/x86/hscale_fast_bilinear_simd.c "add %%"REG_a", %%"REG_D" \n\t"\ REG_D 279 libswscale/x86/hscale_fast_bilinear_simd.c : "%"REG_a, "%"REG_c, "%"REG_d, "%"REG_S, "%"REG_D REG_D 319 libswscale/x86/hscale_fast_bilinear_simd.c "mov %1, %%"REG_D" \n\t" REG_D 333 libswscale/x86/hscale_fast_bilinear_simd.c "mov %6, %%"REG_D" \n\t" // buf2 REG_D 363 libswscale/x86/hscale_fast_bilinear_simd.c : "%"REG_a, "%"REG_c, "%"REG_d, "%"REG_S, "%"REG_D