root/src/mips/cpu-mips.cc

DEFINITIONS

1. SetUp
2. SupportsCrankshaft
3. FlushICache
4. DebugBreak

// Copyright 2012 the V8 project authors. All rights reserved.
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// modification, are permitted provided that the following conditions are
// met:
//
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// CPU specific code for arm independent of OS goes here.

#include <sys/syscall.h>
#include <unistd.h>

#ifdef __mips
#include <asm/cachectl.h>
#endif  // #ifdef __mips

#include "v8.h"

#if defined(V8_TARGET_ARCH_MIPS)

#include "cpu.h"
#include "macro-assembler.h"

#include "simulator.h"  // For cache flushing.

namespace v8 {
namespace internal {


void CPU::SetUp() {
  CpuFeatures::Probe();
}


bool CPU::SupportsCrankshaft() {
  return CpuFeatures::IsSupported(FPU);
}


void CPU::FlushICache(void* start, size_t size) {
  // Nothing to do, flushing no instructions.
  if (size == 0) {
    return;
  }

#if !defined (USE_SIMULATOR)
#if defined(ANDROID)
  // Bionic cacheflush can typically run in userland, avoiding kernel call.
  char *end = reinterpret_cast<char *>(start) + size;
  cacheflush(
    reinterpret_cast<intptr_t>(start), reinterpret_cast<intptr_t>(end), 0);
#else  // ANDROID
  int res;
  // See http://www.linux-mips.org/wiki/Cacheflush_Syscall.
  res = syscall(__NR_cacheflush, start, size, ICACHE);
  if (res) {
    V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache");
  }
#endif  // ANDROID
#else  // USE_SIMULATOR.
  // Not generating mips instructions for C-code. This means that we are
  // building a mips emulator based target.  We should notify the simulator
  // that the Icache was flushed.
  // None of this code ends up in the snapshot so there are no issues
  // around whether or not to generate the code when building snapshots.
  Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
#endif  // USE_SIMULATOR.
}


void CPU::DebugBreak() {
#ifdef __mips
  asm volatile("break");
#endif  // #ifdef __mips
}


} }  // namespace v8::internal

#endif  // V8_TARGET_ARCH_MIPS