R0 60 nanojit/NativeARM.cpp const Register Assembler::argRegs[] = { R0, R1, R2, R3 };
R0 61 nanojit/NativeARM.cpp const Register Assembler::retRegs[] = { R0, R1 };
R0 571 nanojit/NativeARM.cpp MOV(R0, IP);
R0 662 nanojit/NativeARM.cpp NanoAssert( ((ra == R0) && (rb == R1)) || ((ra == R2) && (rb == R3)) );
R0 889 nanojit/NativeARM.cpp STR(R0, FP, d+0);
R0 896 nanojit/NativeARM.cpp FMDRR(rr, R0, R1);
R0 931 nanojit/NativeARM.cpp Register r = R0;
R0 971 nanojit/NativeARM.cpp rmask(R0) | rmask(R1) | rmask(R2) | rmask(R3) | rmask(R4) |
R0 1176 nanojit/NativeARM.cpp prefer = rmask(R0);
R0 2625 nanojit/NativeARM.cpp MOV(IP, R0);
R0 2633 nanojit/NativeARM.cpp findSpecificRegFor(value, R0);
R0 2639 nanojit/NativeARM.cpp FMRRD(R0, R1, reg);
R0 2642 nanojit/NativeARM.cpp findSpecificRegFor(value->oprnd1(), R0); // lo
R0 183 nanojit/NativeARM.h static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10;
R0 198 nanojit/NativeARM.h #define firstreg() R0
R0 106 nanojit/NativePPC.cpp STPUX(SP, SP, R0);
R0 107 nanojit/NativePPC.cpp asm_li(R0, -aligned);
R0 113 nanojit/NativePPC.cpp STP(R0, lr_offset, SP); // save LR in linkage.lr
R0 114 nanojit/NativePPC.cpp MFLR(R0);
R0 121 nanojit/NativePPC.cpp MTLR(R0);
R0 122 nanojit/NativePPC.cpp LP(R0, lr_offset, SP);
R0 155 nanojit/NativePPC.cpp LBZX(rr, ra, R0); // rr = [ra+R0]
R0 156 nanojit/NativePPC.cpp asm_li(R0,d);
R0 165 nanojit/NativePPC.cpp LHZX(rr, ra, R0); // rr = [ra+R0]
R0 166 nanojit/NativePPC.cpp asm_li(R0,d);
R0 175 nanojit/NativePPC.cpp LWZX(rr, ra, R0); // rr = [ra+R0]
R0 176 nanojit/NativePPC.cpp asm_li(R0,d);
R0 217 nanojit/NativePPC.cpp STWX(rs, ra, R0);
R0 218 nanojit/NativePPC.cpp asm_li(R0, dr);
R0 264 nanojit/NativePPC.cpp LDX(rr, ra, R0);
R0 265 nanojit/NativePPC.cpp asm_li(R0, dr);
R0 279 nanojit/NativePPC.cpp LFDX(rr, ra, R0);
R0 280 nanojit/NativePPC.cpp asm_li(R0, dr);
R0 334 nanojit/NativePPC.cpp STW(R0, dr, ra); // hi
R0 335 nanojit/NativePPC.cpp asm_li(R0, int32_t(q>>32)); // hi
R0 336 nanojit/NativePPC.cpp STW(R0, dr+4, ra); // lo
R0 337 nanojit/NativePPC.cpp asm_li(R0, int32_t(q)); // lo
R0 372 nanojit/NativePPC.cpp STDX(rs, ra, R0);
R0 373 nanojit/NativePPC.cpp asm_li(R0, dr);
R0 387 nanojit/NativePPC.cpp STFDX(rs, ra, R0);
R0 388 nanojit/NativePPC.cpp asm_li(R0, dr);
R0 554 nanojit/NativePPC.cpp MTCTR(R0);
R0 555 nanojit/NativePPC.cpp asm_li32(R0, (int)targ);
R0 557 nanojit/NativePPC.cpp MTCTR(R0);
R0 559 nanojit/NativePPC.cpp asm_li64(R0, uint64_t(targ));
R0 561 nanojit/NativePPC.cpp asm_li32(R0, uint32_t(uintptr_t(targ)));
R0 933 nanojit/NativePPC.cpp case LIR_lsh: SLW(rr, ra, R0); ANDI(R0, rb, 31); break;
R0 934 nanojit/NativePPC.cpp case LIR_rsh: SRAW(rr, ra, R0); ANDI(R0, rb, 31); break;
R0 935 nanojit/NativePPC.cpp case LIR_ush: SRW(rr, ra, R0); ANDI(R0, rb, 31); break;
R0 939 nanojit/NativePPC.cpp SLD(rr, ra, R0);
R0 940 nanojit/NativePPC.cpp ANDI(R0, rb, 63);
R0 943 nanojit/NativePPC.cpp SRD(rr, ra, R0);
R0 944 nanojit/NativePPC.cpp ANDI(R0, rb, 63);
R0 947 nanojit/NativePPC.cpp SRAD(rr, ra, R0);
R0 948 nanojit/NativePPC.cpp ANDI(R0, rb, 63);
R0 990 nanojit/NativePPC.cpp STW(R0, d+4, SP);
R0 991 nanojit/NativePPC.cpp XORIS(R0, v, 0x8000);
R0 993 nanojit/NativePPC.cpp STW(R0, d+4, SP);
R0 994 nanojit/NativePPC.cpp LIS(R0, 0x8000);
R0 995 nanojit/NativePPC.cpp STW(R0, d, SP);
R0 996 nanojit/NativePPC.cpp LIS(R0, 0x4330);
R0 1013 nanojit/NativePPC.cpp STW(R0, d+4, SP);
R0 1014 nanojit/NativePPC.cpp LI(R0, 0);
R0 1017 nanojit/NativePPC.cpp STW(R0, d, SP);
R0 1018 nanojit/NativePPC.cpp LIS(R0, 0x4330);
R0 1063 nanojit/NativePPC.cpp STW(R0, 12, SP);
R0 1064 nanojit/NativePPC.cpp asm_li(R0, w.hi);
R0 1065 nanojit/NativePPC.cpp STW(R0, 16, SP);
R0 1066 nanojit/NativePPC.cpp asm_li(R0, w.lo);
R0 1074 nanojit/NativePPC.cpp RLDIMI(r,R0,32,0); // or 32,32?
R0 1075 nanojit/NativePPC.cpp asm_li(R0, int32_t(q>>32)); // hi bits into R0
R0 1376 nanojit/NativePPC.cpp LDX(R2, R2, R0); // R2 = [table + index*8]
R0 1377 nanojit/NativePPC.cpp SLDI(R0, indexreg, 3); // R0 = index*8
R0 1383 nanojit/NativePPC.cpp LWZX(R2, R2, R0); // R2 = [table + index*4]
R0 1384 nanojit/NativePPC.cpp SLWI(R0, indexreg, 2); // R0 = index*4