R1                 60 nanojit/NativeARM.cpp const Register Assembler::argRegs[] = { R0, R1, R2, R3 };
R1                 61 nanojit/NativeARM.cpp const Register Assembler::retRegs[] = { R0, R1 };
R1                649 nanojit/NativeARM.cpp     if ((r == R1) || (r == R3)) {
R1                662 nanojit/NativeARM.cpp         NanoAssert( ((ra == R0) && (rb == R1)) || ((ra == R2) && (rb == R3)) );
R1                890 nanojit/NativeARM.cpp                 STR(R1, FP, d+4);
R1                896 nanojit/NativeARM.cpp                 FMDRR(rr, R0, R1);
R1                971 nanojit/NativeARM.cpp         rmask(R0) | rmask(R1) | rmask(R2) | rmask(R3) | rmask(R4) |
R1               1178 nanojit/NativeARM.cpp         prefer = rmask(R1);
R1               2639 nanojit/NativeARM.cpp             FMRRD(R0, R1, reg);
R1               2643 nanojit/NativeARM.cpp             findSpecificRegFor(value->oprnd2(), R1); // hi
R1                183 nanojit/NativeARM.h static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10;