R2                 60 nanojit/NativeARM.cpp const Register Assembler::argRegs[] = { R0, R1, R2, R3 };
R2                662 nanojit/NativeARM.cpp         NanoAssert( ((ra == R0) && (rb == R1)) || ((ra == R2) && (rb == R3)) );
R2                971 nanojit/NativeARM.cpp         rmask(R0) | rmask(R1) | rmask(R2) | rmask(R3) | rmask(R4) |
R2                183 nanojit/NativeARM.h static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10;
R2               1117 nanojit/NativePPC.cpp             MTCTR(R2);
R2               1118 nanojit/NativePPC.cpp             asm_li64(R2, uintptr_t(addr)); // 5 instructions
R2               1124 nanojit/NativePPC.cpp         MTCTR(R2);
R2               1125 nanojit/NativePPC.cpp         asm_li32(R2, uint32_t(uintptr_t(addr))); // 2 instructions
R2               1375 nanojit/NativePPC.cpp         MTCTR(R2);                              // CTR = R2
R2               1376 nanojit/NativePPC.cpp         LDX(R2, R2, R0);                        // R2 = [table + index*8]
R2               1378 nanojit/NativePPC.cpp         asm_li64(R2, uint64_t(native_table));   // R2 = table (5 instr)
R2               1382 nanojit/NativePPC.cpp         MTCTR(R2);                              // CTR = R2
R2               1383 nanojit/NativePPC.cpp         LWZX(R2, R2, R0);                       // R2 = [table + index*4]
R2               1385 nanojit/NativePPC.cpp         asm_li(R2, int32_t(native_table));      // R2 = table (up to 2 instructions)