R3 60 nanojit/NativeARM.cpp const Register Assembler::argRegs[] = { R0, R1, R2, R3 }; R3 649 nanojit/NativeARM.cpp if ((r == R1) || (r == R3)) { R3 654 nanojit/NativeARM.cpp if (r < R3) { R3 662 nanojit/NativeARM.cpp NanoAssert( ((ra == R0) && (rb == R1)) || ((ra == R2) && (rb == R3)) ); R3 676 nanojit/NativeARM.cpp } else if (r == R3) { R3 971 nanojit/NativeARM.cpp rmask(R0) | rmask(R1) | rmask(R2) | rmask(R3) | rmask(R4) | R3 183 nanojit/NativeARM.h static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10; R3 46 nanojit/NativePPC.cpp const Register Assembler::retRegs[] = { R3, R4 }; // high=R3, low=R4 R3 47 nanojit/NativePPC.cpp const Register Assembler::argRegs[] = { R3, R4, R5, R6, R7, R8, R9, R10 }; R3 630 nanojit/NativePPC.cpp Register r = ins->isop(LIR_ret) ? R3 : F1; R3 728 nanojit/NativePPC.cpp Register r = R3; R3 1194 nanojit/NativePPC.cpp prefer = rmask(R3);