patch 4875 core/CodegenLIR.cpp Patch& patch = p->head; patch 4876 core/CodegenLIR.cpp AvmAssert(patch.label->bb != NULL); patch 4877 core/CodegenLIR.cpp if (patch.br->isop(LIR_jtbl)) { patch 4878 core/CodegenLIR.cpp patch.br->setTarget(patch.index, patch.label->bb); patch 4880 core/CodegenLIR.cpp AvmAssert(patch.br->isBranch() && patch.index == 0); patch 4881 core/CodegenLIR.cpp patch.br->setTarget(patch.label->bb); patch 580 nanojit/Assembler.cpp patch(rec); patch 235 nanojit/Assembler.h void patch(GuardRecord *lr); patch 236 nanojit/Assembler.h void patch(SideExit *exit); patch 238 nanojit/Assembler.h void patch(SideExit *exit, SwitchInfo* si); patch 447 nanojit/NativePPC.cpp NIns *patch; patch 451 nanojit/NativePPC.cpp patch = asm_branch_near(onfalse, cond, targ); patch 454 nanojit/NativePPC.cpp patch = asm_branch_far(onfalse, cond, targ); patch 456 nanojit/NativePPC.cpp return patch; patch 463 nanojit/NativePPC.cpp NIns *patch = 0; patch 474 nanojit/NativePPC.cpp patch = _nIns; // this is the patchable branch to the given target patch 514 nanojit/NativePPC.cpp if (!patch) patch 515 nanojit/NativePPC.cpp patch = _nIns; patch 516 nanojit/NativePPC.cpp return patch; patch 1124 nanojit/NativeX64.cpp NIns *patch = _nIns; // addr of instr to patch patch 1126 nanojit/NativeX64.cpp return patch; patch 1196 nanojit/NativeX64.cpp NIns *patch; patch 1204 nanojit/NativeX64.cpp patch = _nIns; patch 1212 nanojit/NativeX64.cpp patch = _nIns; patch 1235 nanojit/NativeX64.cpp patch = _nIns; patch 1238 nanojit/NativeX64.cpp return patch; patch 1725 nanojit/NativeX64.cpp if (patch[0] == 0xE9) { patch 1727 nanojit/NativeX64.cpp next = patch+5; patch 1728 nanojit/NativeX64.cpp } else if (patch[0] == 0x0F && (patch[1] & 0xF0) == 0x80) { patch 1730 nanojit/NativeX64.cpp next = patch+6;