REG 7187 src/arm/code-stubs-arm.cc { REG(r6), REG(r4), REG(r7), EMIT_REMEMBERED_SET },
REG 7188 src/arm/code-stubs-arm.cc { REG(r6), REG(r2), REG(r7), EMIT_REMEMBERED_SET },
REG 7192 src/arm/code-stubs-arm.cc { REG(r3), REG(r4), REG(r5), EMIT_REMEMBERED_SET },
REG 7194 src/arm/code-stubs-arm.cc { REG(r4), REG(r1), REG(r2), OMIT_REMEMBERED_SET },
REG 7196 src/arm/code-stubs-arm.cc { REG(r1), REG(r2), REG(r3), EMIT_REMEMBERED_SET },
REG 7197 src/arm/code-stubs-arm.cc { REG(r3), REG(r2), REG(r1), EMIT_REMEMBERED_SET },
REG 7199 src/arm/code-stubs-arm.cc { REG(r2), REG(r1), REG(r3), EMIT_REMEMBERED_SET },
REG 7200 src/arm/code-stubs-arm.cc { REG(r3), REG(r1), REG(r2), EMIT_REMEMBERED_SET },
REG 7202 src/arm/code-stubs-arm.cc { REG(r3), REG(r2), REG(r4), EMIT_REMEMBERED_SET },
REG 7203 src/arm/code-stubs-arm.cc { REG(r2), REG(r3), REG(r4), EMIT_REMEMBERED_SET },
REG 7207 src/arm/code-stubs-arm.cc { REG(r2), REG(r3), REG(r9), EMIT_REMEMBERED_SET },
REG 7208 src/arm/code-stubs-arm.cc { REG(r2), REG(r3), REG(r9), OMIT_REMEMBERED_SET },
REG 7210 src/arm/code-stubs-arm.cc { REG(r6), REG(r2), REG(r0), EMIT_REMEMBERED_SET },
REG 7211 src/arm/code-stubs-arm.cc { REG(r2), REG(r6), REG(r9), EMIT_REMEMBERED_SET },
REG 7213 src/arm/code-stubs-arm.cc { REG(r5), REG(r0), REG(r6), EMIT_REMEMBERED_SET },
REG 7215 src/arm/code-stubs-arm.cc { REG(r2), REG(r4), REG(r1), EMIT_REMEMBERED_SET },
REG 7217 src/arm/code-stubs-arm.cc { REG(no_reg), REG(no_reg), REG(no_reg), EMIT_REMEMBERED_SET}
REG 7122 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(eax), REG(edi), EMIT_REMEMBERED_SET },
REG 7124 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(ecx), REG(edx), EMIT_REMEMBERED_SET },
REG 7125 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(edi), REG(edx), OMIT_REMEMBERED_SET },
REG 7127 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(ecx), REG(edx), OMIT_REMEMBERED_SET },
REG 7130 src/ia32/code-stubs-ia32.cc { REG(edx), REG(ecx), REG(ebx), EMIT_REMEMBERED_SET },
REG 7133 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(ecx), REG(edx), EMIT_REMEMBERED_SET },
REG 7135 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(edi), REG(edx), EMIT_REMEMBERED_SET },
REG 7137 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(edx), REG(ecx), EMIT_REMEMBERED_SET},
REG 7139 src/ia32/code-stubs-ia32.cc { REG(edi), REG(ebx), REG(ecx), EMIT_REMEMBERED_SET},
REG 7140 src/ia32/code-stubs-ia32.cc { REG(edx), REG(edi), REG(ebx), EMIT_REMEMBERED_SET},
REG 7144 src/ia32/code-stubs-ia32.cc { REG(edx), REG(ebx), REG(edi), EMIT_REMEMBERED_SET},
REG 7145 src/ia32/code-stubs-ia32.cc { REG(edx), REG(ebx), REG(edi), OMIT_REMEMBERED_SET},
REG 7147 src/ia32/code-stubs-ia32.cc { REG(eax), REG(edx), REG(esi), EMIT_REMEMBERED_SET},
REG 7148 src/ia32/code-stubs-ia32.cc { REG(edx), REG(eax), REG(edi), EMIT_REMEMBERED_SET},
REG 7150 src/ia32/code-stubs-ia32.cc { REG(ebx), REG(eax), REG(ecx), EMIT_REMEMBERED_SET},
REG 7152 src/ia32/code-stubs-ia32.cc { REG(ecx), REG(edx), REG(ebx), EMIT_REMEMBERED_SET},
REG 7154 src/ia32/code-stubs-ia32.cc { REG(no_reg), REG(no_reg), REG(no_reg), EMIT_REMEMBERED_SET}
REG 7436 src/mips/code-stubs-mips.cc { REG(s2), REG(s0), REG(t3), EMIT_REMEMBERED_SET },
REG 7437 src/mips/code-stubs-mips.cc { REG(s2), REG(a2), REG(t3), EMIT_REMEMBERED_SET },
REG 7441 src/mips/code-stubs-mips.cc { REG(a3), REG(t0), REG(t1), EMIT_REMEMBERED_SET },
REG 7443 src/mips/code-stubs-mips.cc { REG(t0), REG(a1), REG(a2), OMIT_REMEMBERED_SET },
REG 7445 src/mips/code-stubs-mips.cc { REG(a1), REG(a2), REG(a3), EMIT_REMEMBERED_SET },
REG 7446 src/mips/code-stubs-mips.cc { REG(a3), REG(a2), REG(a1), EMIT_REMEMBERED_SET },
REG 7448 src/mips/code-stubs-mips.cc { REG(a2), REG(a1), REG(a3), EMIT_REMEMBERED_SET },
REG 7449 src/mips/code-stubs-mips.cc { REG(a3), REG(a1), REG(a2), EMIT_REMEMBERED_SET },
REG 7451 src/mips/code-stubs-mips.cc { REG(a3), REG(a2), REG(t0), EMIT_REMEMBERED_SET },
REG 7452 src/mips/code-stubs-mips.cc { REG(a2), REG(a3), REG(t0), EMIT_REMEMBERED_SET },
REG 7456 src/mips/code-stubs-mips.cc { REG(a2), REG(a3), REG(t5), EMIT_REMEMBERED_SET },
REG 7457 src/mips/code-stubs-mips.cc { REG(a2), REG(a3), REG(t5), OMIT_REMEMBERED_SET },
REG 7459 src/mips/code-stubs-mips.cc { REG(t2), REG(a2), REG(a0), EMIT_REMEMBERED_SET },
REG 7460 src/mips/code-stubs-mips.cc { REG(a2), REG(t2), REG(t5), EMIT_REMEMBERED_SET },
REG 7462 src/mips/code-stubs-mips.cc { REG(t1), REG(a0), REG(t2), EMIT_REMEMBERED_SET },
REG 7464 src/mips/code-stubs-mips.cc { REG(a2), REG(t0), REG(a1), EMIT_REMEMBERED_SET },
REG 7466 src/mips/code-stubs-mips.cc { REG(no_reg), REG(no_reg), REG(no_reg), EMIT_REMEMBERED_SET}
REG 6068 src/x64/code-stubs-x64.cc { REG(rbx), REG(rax), REG(rdi), EMIT_REMEMBERED_SET },
REG 6070 src/x64/code-stubs-x64.cc { REG(rbx), REG(rcx), REG(rdx), EMIT_REMEMBERED_SET },
REG 6072 src/x64/code-stubs-x64.cc { REG(rbx), REG(rcx), REG(rdx), OMIT_REMEMBERED_SET },
REG 6075 src/x64/code-stubs-x64.cc { REG(rdx), REG(rcx), REG(rbx), EMIT_REMEMBERED_SET },
REG 6078 src/x64/code-stubs-x64.cc { REG(rbx), REG(rcx), REG(rdx), EMIT_REMEMBERED_SET },
REG 6080 src/x64/code-stubs-x64.cc { REG(rbx), REG(r8), REG(r9), EMIT_REMEMBERED_SET },
REG 6082 src/x64/code-stubs-x64.cc { REG(rbx), REG(rdx), REG(rcx), EMIT_REMEMBERED_SET},
REG 6084 src/x64/code-stubs-x64.cc { REG(rdi), REG(rbx), REG(rcx), EMIT_REMEMBERED_SET},
REG 6085 src/x64/code-stubs-x64.cc { REG(rdx), REG(rdi), REG(rbx), EMIT_REMEMBERED_SET},
REG 6089 src/x64/code-stubs-x64.cc { REG(rdx), REG(rbx), REG(rdi), EMIT_REMEMBERED_SET},
REG 6090 src/x64/code-stubs-x64.cc { REG(rdx), REG(rbx), REG(rdi), OMIT_REMEMBERED_SET},
REG 6093 src/x64/code-stubs-x64.cc { REG(rdx), REG(r11), REG(r15), EMIT_REMEMBERED_SET},
REG 6095 src/x64/code-stubs-x64.cc { REG(r11), REG(rax), REG(r15), EMIT_REMEMBERED_SET},
REG 6097 src/x64/code-stubs-x64.cc { REG(rbx), REG(rax), REG(rcx), EMIT_REMEMBERED_SET},
REG 6099 src/x64/code-stubs-x64.cc { REG(rcx), REG(rdx), REG(rbx), EMIT_REMEMBERED_SET},
REG 6101 src/x64/code-stubs-x64.cc { REG(no_reg), REG(no_reg), REG(no_reg), EMIT_REMEMBERED_SET}
REG 819 src/x64/macro-assembler-x64.cc REG(rax), REG(rcx), REG(rdx), REG(rbx), REG(rbp), REG(rsi), REG(rdi), REG(r8),
REG 820 src/x64/macro-assembler-x64.cc REG(r9), REG(r10), REG(r11)