REG_OPER_OP_ORDER 59 src/ia32/disasm-ia32.cc {0x03, "add", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 61 src/ia32/disasm-ia32.cc {0x0B, "or", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 62 src/ia32/disasm-ia32.cc {0x1B, "sbb", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 64 src/ia32/disasm-ia32.cc {0x23, "and", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 66 src/ia32/disasm-ia32.cc {0x2A, "subb", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 67 src/ia32/disasm-ia32.cc {0x2B, "sub", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 69 src/ia32/disasm-ia32.cc {0x33, "xor", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 71 src/ia32/disasm-ia32.cc {0x3A, "cmpb", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 72 src/ia32/disasm-ia32.cc {0x3B, "cmp", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 73 src/ia32/disasm-ia32.cc {0x84, "test_b", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 74 src/ia32/disasm-ia32.cc {0x85, "test", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 75 src/ia32/disasm-ia32.cc {0x87, "xchg", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 76 src/ia32/disasm-ia32.cc {0x8A, "mov_b", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 77 src/ia32/disasm-ia32.cc {0x8B, "mov", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 78 src/ia32/disasm-ia32.cc {0x8D, "lea", REG_OPER_OP_ORDER},
REG_OPER_OP_ORDER 495 src/ia32/disasm-ia32.cc case REG_OPER_OP_ORDER: {
REG_OPER_OP_ORDER 674 src/ia32/disasm-ia32.cc int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
REG_OPER_OP_ORDER 1047 src/ia32/disasm-ia32.cc data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
REG_OPER_OP_ORDER 1165 src/ia32/disasm-ia32.cc data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
REG_OPER_OP_ORDER 66 src/x64/disasm-x64.cc { 0x03, REG_OPER_OP_ORDER, "add" },
REG_OPER_OP_ORDER 70 src/x64/disasm-x64.cc { 0x0B, REG_OPER_OP_ORDER, "or" },
REG_OPER_OP_ORDER 74 src/x64/disasm-x64.cc { 0x13, REG_OPER_OP_ORDER, "adc" },
REG_OPER_OP_ORDER 78 src/x64/disasm-x64.cc { 0x1B, REG_OPER_OP_ORDER, "sbb" },
REG_OPER_OP_ORDER 82 src/x64/disasm-x64.cc { 0x23, REG_OPER_OP_ORDER, "and" },
REG_OPER_OP_ORDER 86 src/x64/disasm-x64.cc { 0x2B, REG_OPER_OP_ORDER, "sub" },
REG_OPER_OP_ORDER 90 src/x64/disasm-x64.cc { 0x33, REG_OPER_OP_ORDER, "xor" },
REG_OPER_OP_ORDER 94 src/x64/disasm-x64.cc { 0x3B, REG_OPER_OP_ORDER, "cmp" },
REG_OPER_OP_ORDER 95 src/x64/disasm-x64.cc { 0x63, REG_OPER_OP_ORDER, "movsxlq" },
REG_OPER_OP_ORDER 97 src/x64/disasm-x64.cc { 0x85, REG_OPER_OP_ORDER, "test" },
REG_OPER_OP_ORDER 99 src/x64/disasm-x64.cc { 0x87, REG_OPER_OP_ORDER, "xchg" },
REG_OPER_OP_ORDER 103 src/x64/disasm-x64.cc { 0x8B, REG_OPER_OP_ORDER, "mov" },
REG_OPER_OP_ORDER 104 src/x64/disasm-x64.cc { 0x8D, REG_OPER_OP_ORDER, "lea" },
REG_OPER_OP_ORDER 278 src/x64/disasm-x64.cc {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 279 src/x64/disasm-x64.cc {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 280 src/x64/disasm-x64.cc {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 281 src/x64/disasm-x64.cc {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 282 src/x64/disasm-x64.cc {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 283 src/x64/disasm-x64.cc {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 284 src/x64/disasm-x64.cc {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 285 src/x64/disasm-x64.cc {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 286 src/x64/disasm-x64.cc {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 287 src/x64/disasm-x64.cc {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 288 src/x64/disasm-x64.cc {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 289 src/x64/disasm-x64.cc {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 290 src/x64/disasm-x64.cc {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 291 src/x64/disasm-x64.cc {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 292 src/x64/disasm-x64.cc {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
REG_OPER_OP_ORDER 293 src/x64/disasm-x64.cc {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
REG_OPER_OP_ORDER 619 src/x64/disasm-x64.cc case REG_OPER_OP_ORDER: {
REG_OPER_OP_ORDER 1254 src/x64/disasm-x64.cc current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);