ROR               185 src/arm/assembler-arm.cc   ASSERT(shift_op != ROR || shift_imm != 0);  // use RRX if you mean it
ROR               193 src/arm/assembler-arm.cc     shift_op_ = ROR;
ROR               224 src/arm/disasm-arm.cc     if ((shift == ROR) && (shift_amount == 0)) {
ROR              1421 src/arm/simulator-arm.cc     if ((shift == ROR) && (shift_amount == 0)) {
ROR              1470 src/arm/simulator-arm.cc       case ROR: {
ROR              1542 src/arm/simulator-arm.cc       case ROR: {
ROR               165 test/cctest/test-disasm-arm.cc   COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi),
ROR               167 test/cctest/test-disasm-arm.cc   COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)),
ROR               171 test/cctest/test-disasm-arm.cc   COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi),
ROR               192 test/cctest/test-disasm-arm.cc   COMPARE(teq(r7, Operand(r5, ROR, r0), lt),
ROR               194 test/cctest/test-disasm-arm.cc   COMPARE(teq(r7, Operand(r6, ROR, lr)),
ROR               198 test/cctest/test-disasm-arm.cc   COMPARE(teq(r7, Operand(r8, ROR, r1)),
ROR               212 test/cctest/test-disasm-arm.cc   COMPARE(cmn(r1, Operand(r6, ROR, 1)),