op 63 core/AbcGen.h int op = kindToPushOp[kind];
op 64 core/AbcGen.h bytes.add((byte)op);
op 65 core/AbcGen.h if(opcodeInfo[op].operandCount > 0)
op 68 core/CodegenLIR-inlines.h REALLY_INLINE LIns* CodegenLIR::loadIns(LOpcode op, int32_t disp, LIns *base)
op 71 core/CodegenLIR-inlines.h return lirout->insLoad(op, base, (int32_t)disp);
op 74 core/CodegenLIR-inlines.h REALLY_INLINE LIns* CodegenLIR::Ins(LOpcode op)
op 76 core/CodegenLIR-inlines.h return lirout->ins0(op);
op 79 core/CodegenLIR-inlines.h REALLY_INLINE LIns* CodegenLIR::Ins(LOpcode op, LIns *a)
op 81 core/CodegenLIR-inlines.h return lirout->ins1(op, a);
op 94 core/CodegenLIR-inlines.h REALLY_INLINE LIns* CodegenLIR::binaryIns(LOpcode op, LIns *a, LIns *b)
op 96 core/CodegenLIR-inlines.h return lirout->ins2(op,a,b);
op 228 core/CodegenLIR.cpp LOpcode op;
op 341 core/CodegenLIR.cpp LIns *ins1(LOpcode op, LIns *a) {
op 342 core/CodegenLIR.cpp switch (op) {
op 350 core/CodegenLIR.cpp return out->ins1(op, split(a));
op 352 core/CodegenLIR.cpp return out->ins1(op, a);
op 356 core/CodegenLIR.cpp LIns *ins2(LOpcode op, LIns *a, LIns *b) {
op 357 core/CodegenLIR.cpp switch (op) {
op 377 core/CodegenLIR.cpp return out->ins2(op, a, b);
op 706 core/CodegenLIR.cpp switch (op) {
op 713 core/CodegenLIR.cpp return out->ins0(op);
op 729 core/CodegenLIR.cpp switch (op) {
op 753 core/CodegenLIR.cpp return out->ins1(op, a);
op 757 core/CodegenLIR.cpp switch (op) {
op 806 core/CodegenLIR.cpp return out->ins2(op, a, b);
op 810 core/CodegenLIR.cpp switch (op) {
op 821 core/CodegenLIR.cpp return out->ins3(op, a, b, c);
op 825 core/CodegenLIR.cpp switch (op) {
op 849 core/CodegenLIR.cpp return out->insLoad(op, base, disp);
op 854 core/CodegenLIR.cpp return out->insStore(op, value, base, d);
op 858 core/CodegenLIR.cpp switch (op) {
op 864 core/CodegenLIR.cpp return out->insBranch(op, cond, to);
op 965 core/CodegenLIR.cpp val = out->insLoad(op, base, d);
op 970 core/CodegenLIR.cpp return out->insLoad(op, base, d);
op 978 core/CodegenLIR.cpp return out->insStore(op, value, base, d);
op 982 core/CodegenLIR.cpp if (op == LIR_label) {
op 986 core/CodegenLIR.cpp return out->ins0(op);
op 1060 core/CodegenLIR.cpp return (op & ~1) == LIR_i2f;
op 1083 core/CodegenLIR.cpp LOpcode op = v->opcode();
op 1084 core/CodegenLIR.cpp if (isPromote(op))
op 1086 core/CodegenLIR.cpp if (op == LIR_fadd || op == LIR_fsub || op == LIR_fmul) {
op 1092 core/CodegenLIR.cpp return out->ins2(f64arith_to_i32arith(op), a, b);
op 1094 core/CodegenLIR.cpp else if (op == LIR_quad) {
op 1220 core/CodegenLIR.cpp return out->insStore(op, value, base, d);
op 3098 core/CodegenLIR.cpp LOpcode op;
op 3100 core/CodegenLIR.cpp case BUILTIN_number: op = LIR_ldq; break;
op 3103 core/CodegenLIR.cpp case BUILTIN_boolean: op = LIR_ld; break;
op 3104 core/CodegenLIR.cpp default: op = LIR_ldp; break;
op 3106 core/CodegenLIR.cpp return loadIns(op, offset, ptr);
op 3274 core/CodegenLIR.cpp LIns* i2 = loadIns(mi.op, disp, realAddr);
op 3296 core/CodegenLIR.cpp lirout->insStore(mi.op, svalue, realAddr, disp);
op 3509 core/CodegenLIR.cpp LOpcode op;
op 3512 core/CodegenLIR.cpp case OP_divide: op = LIR_fdiv; break;
op 3513 core/CodegenLIR.cpp case OP_multiply: op = LIR_fmul; break;
op 3514 core/CodegenLIR.cpp case OP_subtract: op = LIR_fsub; break;
op 3516 core/CodegenLIR.cpp localSet(sp-1, binaryIns(op, localGetq(sp-1), localGetq(sp)), result);
op 3530 core/CodegenLIR.cpp LOpcode op;
op 3533 core/CodegenLIR.cpp case OP_bitxor: op = LIR_xor; break;
op 3534 core/CodegenLIR.cpp case OP_bitor: op = LIR_or; break;
op 3535 core/CodegenLIR.cpp case OP_bitand: op = LIR_and; break;
op 3536 core/CodegenLIR.cpp case OP_urshift: op = LIR_ush; break;
op 3537 core/CodegenLIR.cpp case OP_rshift: op = LIR_rsh; break;
op 3538 core/CodegenLIR.cpp case OP_lshift: op = LIR_lsh; break;
op 3539 core/CodegenLIR.cpp case OP_multiply_i: op = LIR_mul; break;
op 3540 core/CodegenLIR.cpp case OP_add_i: op = LIR_add; break;
op 3541 core/CodegenLIR.cpp case OP_subtract_i: op = LIR_sub; break;
op 3545 core/CodegenLIR.cpp LIns* out = binaryIns(op, lhs, rhs);
op 4998 core/CodegenLIR.cpp LOpcode const op = mopAddr->opcode();
op 4999 core/CodegenLIR.cpp if (op != LIR_add && op != LIR_sub)
op 5009 core/CodegenLIR.cpp if (op == LIR_sub)
op 5015 core/CodegenLIR.cpp if (op == LIR_sub)
op 5197 core/CodegenLIR.cpp op = LOpcode(op ^ 1);
op 5200 core/CodegenLIR.cpp if ((op == LIR_jt && cond->imm32()) || (op == LIR_jf && !cond->imm32())) {
op 5202 core/CodegenLIR.cpp op = LIR_j;
op 5211 core/CodegenLIR.cpp return lirout->insBranch(op, cond, 0);
op 5215 core/CodegenLIR.cpp LIns *br = branchIns(op, cond);
op 5325 core/CodegenLIR.cpp LOpcode op = i->opcode();
op 5326 core/CodegenLIR.cpp switch (op) {
op 5427 core/CodegenLIR.cpp LOpcode op = i->opcode();
op 5428 core/CodegenLIR.cpp switch (op) {
op 5441 core/CodegenLIR.cpp LIns* prevIns = (LIns*) (uintptr_t(i) - lirSizes[op]);
op 424 core/CodegenLIR.h LIns *branchIns(LOpcode op, LIns *cond);
op 425 core/CodegenLIR.h LIns *branchIns(LOpcode op, LIns *cond, int target_off);
op 459 core/CodegenLIR.h LIns *loadIns(LOpcode op, int32_t disp, LIns *base);
op 460 core/CodegenLIR.h LIns *Ins(LOpcode op);
op 461 core/CodegenLIR.h LIns *Ins(LOpcode op, LIns *a);
op 464 core/CodegenLIR.h LIns *binaryIns(LOpcode op, LIns *a, LIns *b);
op 876 core/Interpreter.cpp # define INSTR(op) L_##op: VERBOSE;
op 879 core/Interpreter.cpp # define INSTR(op) case WOP_##op: L_ ## op: VERBOSE;
op 882 core/Interpreter.cpp # define INSTR(op) L_ ## op: VERBOSE;
op 892 core/Interpreter.cpp # define INSTR(op) case WOP_##op: VERBOSE;
op 915 core/Interpreter.cpp # define INSTR(op) case OP_##op: VERBOSE;
op 1672 core/Interpreter.cpp dest = (CLAMP_32((a1) op (a2)) | tag); \
op 1678 core/Interpreter.cpp dest = core->intToAtom((int32_t)(i1 op i2)); \
op 1270 core/WordcodeEmitter.cpp uintptr_t op = S[i];
op 1271 core/WordcodeEmitter.cpp uintptr_t width = calculateInstructionWidth(op);
op 1273 core/WordcodeEmitter.cpp if (isJumpInstruction(op)) {
op 1319 core/WordcodeEmitter.cpp peep((uint32_t)op, dest-width);
op 224 eval/eval-cogen-expr.cpp bool is_assign = op == OPR_assign || op == OPR_init;
op 240 eval/eval-cogen-expr.cpp cogen->I_opcode(cogen->binopToOpcode(op, &isNegated));
op 250 eval/eval-cogen-expr.cpp if (op == OPR_assign)
op 260 eval/eval-cogen-expr.cpp if (op == OPR_logicalAnd) {
op 273 eval/eval-cogen-expr.cpp else if (op == OPR_logicalOr) {
op 286 eval/eval-cogen-expr.cpp else if (op == OPR_comma) {
op 295 eval/eval-cogen-expr.cpp cogen->I_opcode(cogen->binopToOpcode(op, &isNegated));
op 304 eval/eval-cogen-expr.cpp switch (op) {
op 73 eval/eval-cogen-inlines.h *isNegated = binopMapping[op].isNegated;
op 74 eval/eval-cogen-inlines.h return (AbcOpcode)(binopMapping[op].abcOpcode);
op 225 eval/eval-cogen.h AbcOpcode binopToOpcode(Binop op, bool* isNegated);
op 239 eval/eval-cogen.h void callMN(AbcOpcode op, uint32_t index, uint32_t nargs);
op 240 eval/eval-cogen.h void propU30(AbcOpcode op, uint32_t index);
op 241 eval/eval-cogen.h void emitOp(AbcOpcode op);
op 242 eval/eval-cogen.h void emitOpU30(AbcOpcode op, uint32_t u30);
op 243 eval/eval-cogen.h void emitOpU30Special(AbcOpcode op, uint32_t u30, uint32_t stack_adjust);
op 244 eval/eval-cogen.h void emitOpU30U30(AbcOpcode op, uint32_t u30_1, uint32_t u30_2);
op 245 eval/eval-cogen.h void emitOpU8(AbcOpcode op, uint8_t b);
op 246 eval/eval-cogen.h void emitOpS8(AbcOpcode op, int8_t b);
op 247 eval/eval-cogen.h void emitOpS16(AbcOpcode op, uint16_t s);
op 248 eval/eval-cogen.h void emitJump(AbcOpcode op, Label* label);
op 464 eval/eval-parse.h AssignExpr(Binop op, Expr* lhs, Expr* rhs) : op(op), lhs(lhs), rhs(rhs) {}
op 466 eval/eval-parse.h const Binop op;
op 473 eval/eval-parse.h BinaryExpr(Binop op, Expr* lhs, Expr* rhs) : op(op), lhs(lhs), rhs(rhs) {}
op 475 eval/eval-parse.h const Binop op;
op 482 eval/eval-parse.h UnaryExpr(Unop op, Expr* expr) : op(op), expr(expr) {}
op 485 eval/eval-parse.h Unop const op;
op 348 nanojit/Assembler.cpp if (isValidDisplacement(op, d2)) {
op 965 nanojit/Assembler.cpp LOpcode op = ins->opcode();
op 966 nanojit/Assembler.cpp switch(op)
op 969 nanojit/Assembler.cpp NanoAssertMsgf(false, "unsupported LIR instruction: %d\n", op);
op 1174 nanojit/Assembler.cpp asm_store32(op, ins->oprnd1(), ins->disp(), ins->oprnd2());
op 1184 nanojit/Assembler.cpp if (value->isop(LIR_qjoin) && op != LIR_st32f)
op 1192 nanojit/Assembler.cpp asm_store64(op, value, dr, base);
op 1238 nanojit/Assembler.cpp asm_branch(op == LIR_jf, cond, label->addr);
op 1252 nanojit/Assembler.cpp NIns *branch = asm_branch(op == LIR_jf, cond, 0);
op 1362 nanojit/Assembler.cpp asm_branch(op == LIR_xf, cond, exit);
op 1471 nanojit/Assembler.cpp names->formatIns(ins->oprnd1()), lirNames[op]);
op 1476 nanojit/Assembler.cpp names->formatIns(ins->oprnd1()), lirNames[op]);
op 275 nanojit/Assembler.h Register getBaseReg(LOpcode op, LIns *i, int &d, RegisterMask allow);
op 341 nanojit/Assembler.h void asm_store32(LOpcode op, LIns *val, int d, LIns *base);
op 342 nanojit/Assembler.h void asm_store64(LOpcode op, LIns *val, int d, LIns *base);
op 68 nanojit/LIR.cpp #op,
op 230 nanojit/LIR.cpp base = insDisp(op, base, d);
op 233 nanojit/LIR.cpp ins->initLInsSti(op, val, base, d);
op 241 nanojit/LIR.cpp ins->initLInsOp0(op);
op 249 nanojit/LIR.cpp ins->initLInsOp1(op, o1);
op 257 nanojit/LIR.cpp ins->initLInsOp2(op, o1, o2);
op 265 nanojit/LIR.cpp ins->initLInsOp3(op, o1, o2, o3);
op 271 nanojit/LIR.cpp base = insDisp(op, base, d);
op 274 nanojit/LIR.cpp ins->initLInsLd(op, base, d);
op 280 nanojit/LIR.cpp debug_only( if (LIR_x == op || LIR_xbarrier == op) NanoAssert(!c); )
op 281 nanojit/LIR.cpp return ins2(op, c, (LIns*)gr);
op 286 nanojit/LIR.cpp NanoAssert((op == LIR_j && !condition) ||
op 287 nanojit/LIR.cpp ((op == LIR_jf || op == LIR_jt) && condition));
op 288 nanojit/LIR.cpp return ins2(op, condition, toLabel);
op 384 nanojit/LIR.cpp switch (op) {
op 395 nanojit/LIR.cpp switch (op) {
op 854 nanojit/LIR.cpp return out->insLoad(op, insImmPtr((void*)p), 0);
op 856 nanojit/LIR.cpp return out->insLoad(op, base, off);
op 889 nanojit/LIR.cpp LOpcode op = value->isQuad() ? LIR_stqi : LIR_sti;
op 890 nanojit/LIR.cpp return insStore(op, value, base, d);
op 944 nanojit/LIR.cpp LOpcode op = k_callmap[argt & ARGSIZE_MASK_ANY];
op 945 nanojit/LIR.cpp NanoAssert(op != LIR_skip); // LIR_skip here is just an error condition
op 950 nanojit/LIR.cpp if (!ARM_VFP && (op == LIR_fcall || op == LIR_qcall))
op 951 nanojit/LIR.cpp op = LIR_callh;
op 963 nanojit/LIR.cpp ins->initLInsC(op==LIR_callh ? LIR_icall : op, args2, ci);
op 965 nanojit/LIR.cpp ins->initLInsC(op, args2, ci);
op 1132 nanojit/LIR.cpp uint32_t hash = _hash8(0,uint8_t(op));
op 1137 nanojit/LIR.cpp uint32_t hash = _hash8(0,uint8_t(op));
op 1143 nanojit/LIR.cpp uint32_t hash = _hash8(0,uint8_t(op));
op 1150 nanojit/LIR.cpp uint32_t hash = _hash8(0,uint8_t(op));
op 1274 nanojit/LIR.cpp uint32_t hash = hash1(op,a) & bitmask;
op 1278 nanojit/LIR.cpp (ins->opcode() != op || ins->oprnd1() != a))
op 1297 nanojit/LIR.cpp uint32_t hash = hash2(op,a,b) & bitmask;
op 1301 nanojit/LIR.cpp (ins->opcode() != op || ins->oprnd1() != a || ins->oprnd2() != b))
op 1320 nanojit/LIR.cpp uint32_t hash = hash3(op,a,b,c) & bitmask;
op 1324 nanojit/LIR.cpp (ins->opcode() != op || ins->oprnd1() != a || ins->oprnd2() != b || ins->oprnd3() != c))
op 1343 nanojit/LIR.cpp uint32_t hash = hashLoad(op,a,d) & bitmask;
op 1347 nanojit/LIR.cpp (ins->opcode() != op || ins->oprnd1() != a || ins->disp() != d))
op 1749 nanojit/LIR.cpp LOpcode op = i->opcode();
op 1750 nanojit/LIR.cpp switch(op)
op 1754 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %d", formatRef(i), lirNames[op], i->imm32());
op 1759 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %d", formatRef(i), lirNames[op], i->size());
op 1765 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s #%X:%X /* %g */", formatRef(i), lirNames[op],
op 1772 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s #%g", formatRef(i), lirNames[op], i->imm64f());
op 1778 nanojit/LIR.cpp VMPI_sprintf(s, "%s", lirNames[op]);
op 1787 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s [%s] ( ", formatRef(i), lirNames[op], formatRef(i->arg(--argc)));
op 1789 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s #%s ( ", formatRef(i), lirNames[op], call->_name);
op 1800 nanojit/LIR.cpp VMPI_sprintf(s, "%s %s [ ", lirNames[op], formatRef(i->oprnd1()));
op 1820 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %d %s", formatRef(i), lirNames[op],
op 1823 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %d", formatRef(i), lirNames[op], arg);
op 1826 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %d %s", formatRef(i), lirNames[op],
op 1838 nanojit/LIR.cpp VMPI_sprintf(s, "%s %s -> %s", lirNames[op], formatRef(i->oprnd1()),
op 1843 nanojit/LIR.cpp VMPI_sprintf(s, "%s -> %s", lirNames[op],
op 1850 nanojit/LIR.cpp VMPI_sprintf(s, "%s %s", lirNames[op], formatRef(i->oprnd1()));
op 1865 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %s", formatRef(i), lirNames[op], formatRef(i->oprnd1()));
op 1905 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %s, %s", formatRef(i), lirNames[op],
op 1911 nanojit/LIR.cpp VMPI_sprintf(s, "%s (%s), %s", lirNames[op],
op 1918 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %s ? %s : %s", formatRef(i), lirNames[op],
op 1938 nanojit/LIR.cpp VMPI_sprintf(s, "%s = %s %s[%d]", formatRef(i), lirNames[op],
op 1948 nanojit/LIR.cpp VMPI_sprintf(s, "%s %s[%d] = %s", lirNames[op],
op 2277 nanojit/LIR.cpp return out->insStore(op, v, b, d);
op 2289 nanojit/LIR.cpp if (op == LIR_label)
op 2291 nanojit/LIR.cpp return out->ins0(op);
op 122 nanojit/LIR.h inline bool isCseOpcode(LOpcode op) {
op 123 nanojit/LIR.h return (op >= LIR_int && op <= LIR_uge) ||
op 124 nanojit/LIR.h (op >= LIR_quad && op <= LIR_quge);
op 126 nanojit/LIR.h inline bool isRetOpcode(LOpcode op) {
op 127 nanojit/LIR.h return op == LIR_ret || op == LIR_fret;
op 129 nanojit/LIR.h LOpcode f64arith_to_i32arith(LOpcode op);
op 130 nanojit/LIR.h LOpcode i32cmp_to_i64cmp(LOpcode op);
op 459 nanojit/LIR.h LOpcode op = opcode();
op 460 nanojit/LIR.h return (op >= LIR_eq && op <= LIR_uge) ||
op 461 nanojit/LIR.h (op >= LIR_qeq && op <= LIR_quge) ||
op 462 nanojit/LIR.h (op >= LIR_feq && op <= LIR_fge);
op 959 nanojit/LIR.h LInsp insDisp(LOpcode op, LInsp base, int32_t& d) {
op 960 nanojit/LIR.h if (!isValidDisplacement(op, d)) {
op 1005 nanojit/LIR.h virtual LInsp insLoad(LOpcode op, LIns* base, int32_t d) {
op 1006 nanojit/LIR.h return out->insLoad(op, base, d);
op 1008 nanojit/LIR.h virtual LInsp insStore(LOpcode op, LIns* value, LIns* base, int32_t d) {
op 1009 nanojit/LIR.h return out->insStore(op, value, base, d);
op 1034 nanojit/LIR.h LIns* ins2i(LOpcode op, LIns *oprnd1, int32_t);
op 1159 nanojit/LIR.h LIns* insGuard(LOpcode op, LInsp cond, GuardRecord *gr) {
op 1160 nanojit/LIR.h return add_flush(out->insGuard(op,cond,gr));
op 1196 nanojit/LIR.h LIns* insStore(LOpcode op, LInsp v, LInsp b, int32_t d) {
op 1197 nanojit/LIR.h return add(out->insStore(op, v, b, d));
op 1224 nanojit/LIR.h LIns* insLoad(LOpcode op, LInsp base, int32_t off);
op 1321 nanojit/LIR.h LIns* insLoad(LOpcode op, LInsp cond, int32_t d);
op 1323 nanojit/LIR.h LIns* insGuard(LOpcode op, LInsp cond, GuardRecord *gr);
op 1377 nanojit/LIR.h LInsp insLoad(LOpcode op, LInsp base, int32_t disp);
op 1378 nanojit/LIR.h LInsp insStore(LOpcode op, LInsp o1, LInsp o2, int32_t disp);
op 1379 nanojit/LIR.h LInsp ins0(LOpcode op);
op 1380 nanojit/LIR.h LInsp ins1(LOpcode op, LInsp o1);
op 1381 nanojit/LIR.h LInsp ins2(LOpcode op, LInsp o1, LInsp o2);
op 1382 nanojit/LIR.h LInsp ins3(LOpcode op, LInsp o1, LInsp o2, LInsp o3);
op 1388 nanojit/LIR.h LInsp insGuard(LOpcode op, LInsp cond, GuardRecord *gr);
op 1487 nanojit/LIR.h LInsp insStore(LOpcode op, LInsp v, LInsp b, int32_t d);
op 65 nanojit/Native.h LIR_##op = (number),
op 1173 nanojit/NativeARM.cpp uint32_t op = i->opcode();
op 1175 nanojit/NativeARM.cpp if (op==LIR_icall)
op 1177 nanojit/NativeARM.cpp else if (op == LIR_callh)
op 1179 nanojit/NativeARM.cpp else if (op == LIR_param) {
op 1208 nanojit/NativeARM.cpp switch (op) {
op 1375 nanojit/NativeARM.cpp switch (op) {
op 2059 nanojit/NativeARM.cpp LOpcode op = ins->opcode();
op 2061 nanojit/NativeARM.cpp NanoAssert(op >= LIR_fadd && op <= LIR_fdiv);
op 2072 nanojit/NativeARM.cpp switch (op)
op 2087 nanojit/NativeARM.cpp LOpcode op = ins->opcode();
op 2089 nanojit/NativeARM.cpp NanoAssert(op >= LIR_feq && op <= LIR_fge);
op 2094 nanojit/NativeARM.cpp int e_bit = (op != LIR_feq);
op 2258 nanojit/NativeARM.cpp LOpcode op = ins->opcode();
op 2260 nanojit/NativeARM.cpp switch(op)
op 2290 nanojit/NativeARM.cpp LOpcode op = ins->opcode();
op 2322 nanojit/NativeARM.cpp if (rhs->isconst() && op != LIR_mul)
op 2324 nanojit/NativeARM.cpp if ((op == LIR_add || op == LIR_iaddp) && lhs->isop(LIR_ialloc)) {
op 2336 nanojit/NativeARM.cpp switch (op)
op 2370 nanojit/NativeARM.cpp switch (op)
op 2468 nanojit/NativeARM.cpp LOpcode op = ins->opcode();
op 2479 nanojit/NativeARM.cpp if (op == LIR_not)
op 2488 nanojit/NativeARM.cpp LOpcode op = ins->opcode();
op 2493 nanojit/NativeARM.cpp Register ra = getBaseReg(op, base, d, GpRegs);
op 2495 nanojit/NativeARM.cpp switch(op) {
op 188 nanojit/NativeARM.h static inline bool isValidDisplacement(LOpcode op, int32_t d) {
op 189 nanojit/NativeARM.h if (op == LIR_ldcs)
op 316 nanojit/NativeARM.h #define IsOp(op) (((ARM_##op) >= ARM_and) && ((ARM_##op) <= ARM_mvn))
op 323 nanojit/NativeARM.h #define ALUi(cond, op, S, rd, rl, op2imm) ALUi_chk(cond, op, S, rd, rl, op2imm, 1)
op 327 nanojit/NativeARM.h NanoAssert(IsOp(op));\
op 331 nanojit/NativeARM.h *(--_nIns) = (NIns) ((cond)<<28 | OP_IMM | (ARM_##op)<<21 | (S)<<20 | (rl)<<16 | (rd)<<12 | (op2imm));\
op 332 nanojit/NativeARM.h if (ARM_##op == ARM_mov || ARM_##op == ARM_mvn) { \
op 333 nanojit/NativeARM.h asm_output("%s%s%s %s, #0x%X", #op, condNames[cond], (S)?"s":"", gpn(rd), decOp2Imm(op2imm));\
op 334 nanojit/NativeARM.h } else if (ARM_##op >= ARM_tst && ARM_##op <= ARM_cmn) { \
op 336 nanojit/NativeARM.h asm_output("%s%s %s, #0x%X", #op, condNames[cond], gpn(rl), decOp2Imm(op2imm));\
op 338 nanojit/NativeARM.h asm_output("%s%s%s %s, %s, #0x%X", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rl), decOp2Imm(op2imm));\
op 347 nanojit/NativeARM.h #define ALUr(cond, op, S, rd, rl, rr) ALUr_chk(cond, op, S, rd, rl, rr, 1)
op 351 nanojit/NativeARM.h NanoAssert(IsOp(op));\
op 354 nanojit/NativeARM.h *(--_nIns) = (NIns) ((cond)<<28 |(ARM_##op)<<21 | (S)<<20 | (rl)<<16 | (rd)<<12 | (rr));\
op 355 nanojit/NativeARM.h if (ARM_##op == ARM_mov || ARM_##op == ARM_mvn) { \
op 356 nanojit/NativeARM.h asm_output("%s%s%s %s, %s", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rr));\
op 357 nanojit/NativeARM.h } else if (ARM_##op >= ARM_tst && ARM_##op <= ARM_cmn) { \
op 359 nanojit/NativeARM.h asm_output("%s%s %s, %s", #op, condNames[cond], gpn(rl), gpn(rr));\
op 361 nanojit/NativeARM.h asm_output("%s%s%s %s, %s, %s", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rl), gpn(rr));\
op 375 nanojit/NativeARM.h NanoAssert(IsOp(op));\
op 380 nanojit/NativeARM.h *(--_nIns) = (NIns) ((cond)<<28 |(ARM_##op)<<21 | (S)<<20 | (rl)<<16 | (rd)<<12 | (imm)<<7 | (sh)<<4 | (rr));\
op 381 nanojit/NativeARM.h if (ARM_##op == ARM_mov || ARM_##op == ARM_mvn) { \
op 382 nanojit/NativeARM.h asm_output("%s%s%s %s, %s, %s #%d", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rr), shiftNames[sh], (imm));\
op 383 nanojit/NativeARM.h } else if (ARM_##op >= ARM_tst && ARM_##op <= ARM_cmn) { \
op 385 nanojit/NativeARM.h asm_output("%s%s %s, %s, %s #%d", #op, condNames[cond], gpn(rl), gpn(rr), shiftNames[sh], (imm));\
op 387 nanojit/NativeARM.h asm_output("%s%s%s %s, %s, %s, %s #%d", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rl), gpn(rr), shiftNames[sh], (imm));\
op 401 nanojit/NativeARM.h NanoAssert(IsOp(op));\
op 405 nanojit/NativeARM.h *(--_nIns) = (NIns) ((cond)<<28 |(ARM_##op)<<21 | (S)<<20 | (rl)<<16 | (rd)<<12 | (rs)<<8 | (sh)<<4 | (rr));\
op 406 nanojit/NativeARM.h if (ARM_##op == ARM_mov || ARM_##op == ARM_mvn) { \
op 407 nanojit/NativeARM.h asm_output("%s%s%s %s, %s, %s %s", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rr), shiftNames[sh], gpn(rs));\
op 408 nanojit/NativeARM.h } else if (ARM_##op >= ARM_tst && ARM_##op <= ARM_cmn) { \
op 410 nanojit/NativeARM.h asm_output("%s%s %s, %s, %s %s", #op, condNames[cond], gpn(rl), gpn(rr), shiftNames[sh], gpn(rs));\
op 412 nanojit/NativeARM.h asm_output("%s%s%s %s, %s, %s, %s %s", #op, condNames[cond], (S)?"s":"", gpn(rd), gpn(rl), gpn(rr), shiftNames[sh], gpn(rs));\
op 193 nanojit/NativePPC.cpp switch (op) {
op 316 nanojit/NativePPC.cpp switch (op) {
op 392 nanojit/NativePPC.cpp LOpcode op = ins->opcode();
op 397 nanojit/NativePPC.cpp switch (op) {
op 432 nanojit/NativePPC.cpp asm_cmp(op, a, b, cr);
op 853 nanojit/NativePPC.cpp LOpcode op = ins->opcode();
op 864 nanojit/NativePPC.cpp switch (op) {
op 881 nanojit/NativePPC.cpp switch (op) {
op 898 nanojit/NativePPC.cpp switch (op) {
op 913 nanojit/NativePPC.cpp switch (op) {
op 953 nanojit/NativePPC.cpp debug_only(outputf("%s",lirNames[op]);)
op 959 nanojit/NativePPC.cpp LOpcode op = ins->opcode();
op 966 nanojit/NativePPC.cpp switch (op) {
op 972 nanojit/NativePPC.cpp debug_only(outputf("%s",lirNames[op]);)
op 1023 nanojit/NativePPC.cpp LOpcode op = ins->opcode();
op 1026 nanojit/NativePPC.cpp switch (op) {
op 1028 nanojit/NativePPC.cpp debug_only(outputf("%s",lirNames[op]));
op 1191 nanojit/NativePPC.cpp LOpcode op = i->opcode();
op 1193 nanojit/NativePPC.cpp if (op == LIR_icall || op == LIR_qcall)
op 1195 nanojit/NativePPC.cpp else if (op == LIR_fcall)
op 1197 nanojit/NativePPC.cpp else if (op == LIR_param) {
op 1344 nanojit/NativePPC.cpp LOpcode op = ins->opcode();
op 1345 nanojit/NativePPC.cpp switch (op) {
op 1357 nanojit/NativePPC.cpp debug_only(outputf("%s",lirNames[op]));
op 291 nanojit/NativePPC.h void asm_cmp(LOpcode op, LIns *a, LIns *b, ConditionRegister); \
op 323 nanojit/NativePPC.h "%s%s%s cr%d,%p", #op, (lk)?"l":"", (aa)?"a":"", (cr), _nIns+(bd))
op 335 nanojit/NativePPC.h "%sctr%s cr%d", #op, (lk)?"l":"", (cr))
op 346 nanojit/NativePPC.h #define Simple(asm,op) EMIT1(op, "%s", #asm)
op 354 nanojit/NativePPC.h #define ALU2(op, rd, ra, rb, rc) EMIT1(PPC_##op | GPR(rd)<<21 | GPR(ra)<<16 | GPR(rb)<<11 | (rc),\
op 355 nanojit/NativePPC.h "%s%s %s,%s,%s", #op, (rc)?".":"", gpn(rd), gpn(ra), gpn(rb))
op 356 nanojit/NativePPC.h #define BITALU2(op, ra, rs, rb, rc) EMIT1(PPC_##op | GPR(rs)<<21 | GPR(ra)<<16 | GPR(rb)<<11 | (rc),\
op 357 nanojit/NativePPC.h "%s%s %s,%s,%s", #op, (rc)?".":"", gpn(ra), gpn(rs), gpn(rb))
op 358 nanojit/NativePPC.h #define FPUAB(op, d, a, b, rc) EMIT1(PPC_##op | FPR(d)<<21 | FPR(a)<<16 | FPR(b)<<11 | (rc),\
op 359 nanojit/NativePPC.h "%s%s %s,%s,%s", #op, (rc)?".":"", gpn(d), gpn(a), gpn(b))
op 360 nanojit/NativePPC.h #define FPUAC(op, d, a, c, rc) EMIT1(PPC_##op | FPR(d)<<21 | FPR(a)<<16 | FPR(c)<<6 | (rc),\
op 361 nanojit/NativePPC.h "%s%s %s,%s,%s", #op, (rc)?".":"", gpn(d), gpn(a), gpn(c))
op 404 nanojit/NativePPC.h #define ALU1(op, ra, rs, rc) EMIT1(PPC_##op | GPR(rs)<<21 | GPR(ra)<<16 | GPR(rs)<<11 | (rc),\
op 405 nanojit/NativePPC.h "%s%s %s,%s", #op, (rc)?".":"", gpn(ra), gpn(rs))
op 438 nanojit/NativePPC.h EMIT1(PPC_##op | GPR(r)<<21 | GPR(a)<<16 | uint16_t(d), "%s %s,%d(%s)", #op, gpn(r), int16_t(d), gpn(a));\
op 443 nanojit/NativePPC.h EMIT1(PPC_##op | FPR(r)<<21 | GPR(b)<<16 | uint16_t(d), "%s %s,%d(%s)", #op, gpn(r), int16_t(d), gpn(b));\
op 446 nanojit/NativePPC.h #define MEMx(op, r, a, b) EMIT1(PPC_##op | GPR(r)<<21 | GPR(a)<<16 | GPR(b)<<11,\
op 447 nanojit/NativePPC.h "%s %s,%s,%s", #op, gpn(r), gpn(a), gpn(b))
op 448 nanojit/NativePPC.h #define FMEMx(op, r, a, b) EMIT1(PPC_##op | FPR(r)<<21 | GPR(a)<<16 | GPR(b)<<11,\
op 449 nanojit/NativePPC.h "%s %s,%s,%s", #op, gpn(r), gpn(a), gpn(b))
op 451 nanojit/NativePPC.h #define MEMux(op, rs, ra, rb) EMIT1(PPC_##op | GPR(rs)<<21 | GPR(ra)<<16 | GPR(rb)<<11,\
op 452 nanojit/NativePPC.h "%s %s,%s,%s", #op, gpn(rs), gpn(ra), gpn(rb))
op 492 nanojit/NativePPC.h #define ALUI(op,rd,ra,d) EMIT1(PPC_##op | GPR(rd)<<21 | GPR(ra)<<16 | uint16_t(d),\
op 493 nanojit/NativePPC.h "%s %s,%s,%d (0x%x)", #op, gpn(rd), gpn(ra), int16_t(d), int16_t(d))
op 499 nanojit/NativePPC.h #define BITALUI(op,rd,ra,d) EMIT1(PPC_##op | GPR(ra)<<21 | GPR(rd)<<16 | uint16_t(d),\
op 500 nanojit/NativePPC.h "%s %s,%s,%u (0x%x)", #op, gpn(rd), gpn(ra), uint16_t(d), uint16_t(d))
op 520 nanojit/NativePPC.h #define CMPx(op, crfd, ra, rb, l) EMIT1(PPC_##op | (crfd)<<23 | (l)<<21 | GPR(ra)<<16 | GPR(rb)<<11,\
op 521 nanojit/NativePPC.h "%s%c cr%d,%s,%s", #op, (l)?'d':'w', (crfd), gpn(ra), gpn(rb))
op 540 nanojit/NativePPC.h #define FCMPx(op, crfd, ra, rb) EMIT1(PPC_##op | (crfd)<<23 | FPR(ra)<<16 | FPR(rb)<<11,\
op 541 nanojit/NativePPC.h "%s cr%d,%s,%s", #op, (crfd), gpn(ra), gpn(rb))
op 312 nanojit/NativeSparc.cpp switch (op) {
op 413 nanojit/NativeSparc.cpp switch (op) {
op 630 nanojit/NativeSparc.cpp LOpcode op = ins->opcode();
op 633 nanojit/NativeSparc.cpp if (op == LIR_eq)
op 635 nanojit/NativeSparc.cpp else if (op == LIR_ov)
op 637 nanojit/NativeSparc.cpp else if (op == LIR_lt)
op 639 nanojit/NativeSparc.cpp else if (op == LIR_le)
op 641 nanojit/NativeSparc.cpp else if (op == LIR_gt)
op 643 nanojit/NativeSparc.cpp else if (op == LIR_ge)
op 645 nanojit/NativeSparc.cpp else if (op == LIR_ult)
op 647 nanojit/NativeSparc.cpp else if (op == LIR_ule)
op 649 nanojit/NativeSparc.cpp else if (op == LIR_ugt)
op 660 nanojit/NativeSparc.cpp LOpcode op = ins->opcode();
op 666 nanojit/NativeSparc.cpp bool forceReg = (op == LIR_mul || !rhs->isconst());
op 675 nanojit/NativeSparc.cpp else if ((op == LIR_add||op == LIR_iaddp) && lhs->isop(LIR_alloc) && rhs->isconst()) {
op 695 nanojit/NativeSparc.cpp if (op == LIR_add || op == LIR_iaddp)
op 697 nanojit/NativeSparc.cpp else if (op == LIR_sub)
op 699 nanojit/NativeSparc.cpp else if (op == LIR_mul)
op 701 nanojit/NativeSparc.cpp else if (op == LIR_and)
op 703 nanojit/NativeSparc.cpp else if (op == LIR_or)
op 705 nanojit/NativeSparc.cpp else if (op == LIR_xor)
op 707 nanojit/NativeSparc.cpp else if (op == LIR_lsh)
op 709 nanojit/NativeSparc.cpp else if (op == LIR_rsh)
op 711 nanojit/NativeSparc.cpp else if (op == LIR_ush)
op 719 nanojit/NativeSparc.cpp if (op == LIR_add || op == LIR_iaddp) {
op 721 nanojit/NativeSparc.cpp } else if (op == LIR_sub) {
op 723 nanojit/NativeSparc.cpp } else if (op == LIR_and)
op 725 nanojit/NativeSparc.cpp else if (op == LIR_or)
op 727 nanojit/NativeSparc.cpp else if (op == LIR_xor)
op 729 nanojit/NativeSparc.cpp else if (op == LIR_lsh)
op 731 nanojit/NativeSparc.cpp else if (op == LIR_rsh)
op 733 nanojit/NativeSparc.cpp else if (op == LIR_ush)
op 747 nanojit/NativeSparc.cpp LOpcode op = ins->opcode();
op 757 nanojit/NativeSparc.cpp if (op == LIR_not)
op 769 nanojit/NativeSparc.cpp LOpcode op = ins->opcode();
op 774 nanojit/NativeSparc.cpp switch(op) {
op 802 nanojit/NativeSparc.cpp LOpcode op = ins->opcode();
op 808 nanojit/NativeSparc.cpp NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
op 815 nanojit/NativeSparc.cpp if (op == LIR_cmov) {
op 830 nanojit/NativeSparc.cpp } else if (op == LIR_qcmov) {
op 914 nanojit/NativeSparc.cpp LOpcode op = ins->opcode();
op 924 nanojit/NativeSparc.cpp if (op == LIR_fadd)
op 926 nanojit/NativeSparc.cpp else if (op == LIR_fsub)
op 928 nanojit/NativeSparc.cpp else if (op == LIR_fmul)
op 128 nanojit/NativeX64.cpp return op & 255;
op 133 nanojit/NativeX64.cpp int shift = 64 - 8*oplen(op);
op 134 nanojit/NativeX64.cpp uint64_t rex = ((op >> shift) & 255) | ((r&8)>>1) | ((b&8)>>3);
op 135 nanojit/NativeX64.cpp return rex != 0x40 ? op | rex << shift : op - 1;
op 140 nanojit/NativeX64.cpp int shift = 64 - 8*oplen(op);
op 141 nanojit/NativeX64.cpp uint64_t rex = ((op >> shift) & 255) | ((r&8)>>1) | ((x&8)>>2) | ((b&8)>>3);
op 142 nanojit/NativeX64.cpp return rex != 0x40 ? op | rex << shift : op - 1;
op 148 nanojit/NativeX64.cpp int shift = 64 - 8*oplen(op);
op 149 nanojit/NativeX64.cpp uint64_t rex = ((op >> shift) & 255) | ((r&8)>>1) | ((b&8)>>3);
op 150 nanojit/NativeX64.cpp return ((rex | (b & ~3)) != 0x40) ? (op | (rex << shift)) : op - 1;
op 156 nanojit/NativeX64.cpp int shift = 64 - 8*oplen(op) + 8;
op 157 nanojit/NativeX64.cpp uint64_t rex = ((op >> shift) & 255) | ((r&8)>>1) | ((b&8)>>3);
op 159 nanojit/NativeX64.cpp return rex != 0x40 ? op | rex << shift :
op 160 nanojit/NativeX64.cpp ((op & ~(255LL<<shift)) | (op>>(shift-8)&255) << shift) - 1;
op 165 nanojit/NativeX64.cpp return op | uint64_t((r&7)<<3 | (b&7))<<56;
op 170 nanojit/NativeX64.cpp return op | /*modrm*/uint64_t((r&7)<<3)<<48 | /*sib*/uint64_t((x&7)<<3|(b&7))<<56;
op 178 nanojit/NativeX64.cpp NanoAssert((((op>>24)&255)>>6) == 2); // disp32 mode
op 179 nanojit/NativeX64.cpp int len = oplen(op);
op 180 nanojit/NativeX64.cpp op = (op & ~0xff000000LL) | (0x40 | (r&7)<<3 | (b&7))<<24; // replace mod
op 181 nanojit/NativeX64.cpp return op<<24 | int64_t(d)<<56 | (len-3); // shrink disp, add disp8
op 184 nanojit/NativeX64.cpp return op | int64_t(d)<<32 | uint64_t((r&7)<<3 | (b&7))<<24;
op 192 nanojit/NativeX64.cpp int len = oplen(op);
op 197 nanojit/NativeX64.cpp ((int64_t*)_nIns)[-1] = op;
op 204 nanojit/NativeX64.cpp emit(op | uint64_t(v)<<56);
op 212 nanojit/NativeX64.cpp emit(op | uint64_t(offset)<<56);
op 225 nanojit/NativeX64.cpp emit(op | uint64_t(uint32_t(offset))<<32);
op 230 nanojit/NativeX64.cpp emit(rexrxb(mod_rxb(op, r, x, b), r, x, b));
op 235 nanojit/NativeX64.cpp emit(rexrb(mod_rr(op, r, b), r, b));
op 240 nanojit/NativeX64.cpp emit(rexrb8(mod_rr(op, r, b), r, b));
op 245 nanojit/NativeX64.cpp emit(rexprb(mod_rr(op, r, b), r, b));
op 250 nanojit/NativeX64.cpp emit(rexrb8(mod_disp32(op, r, b, d), r, b));
op 255 nanojit/NativeX64.cpp emit(rexrb(mod_disp32(op, r, b, d), r, b));
op 261 nanojit/NativeX64.cpp NanoAssert(((op>>56)&0xC0) == 0x80); // make sure mod bits == 2 == disp32 mode
op 265 nanojit/NativeX64.cpp op ^= 0xC000000000000000LL; // change mod bits to 1 == disp8 mode
op 271 nanojit/NativeX64.cpp return op;
op 276 nanojit/NativeX64.cpp op = emit_disp32(op, d);
op 277 nanojit/NativeX64.cpp emitrr(op, r, b);
op 283 nanojit/NativeX64.cpp op = emit_disp32(op, d);
op 284 nanojit/NativeX64.cpp emitprr(op, r, b);
op 292 nanojit/NativeX64.cpp emitrr(op, r, b);
op 299 nanojit/NativeX64.cpp emitr(op, r);
op 307 nanojit/NativeX64.cpp emitrxb(op, r, x, b);
op 313 nanojit/NativeX64.cpp op |= uint64_t(imm8)<<56 | uint64_t(b&7)<<48; // modrm is 2nd to last byte
op 314 nanojit/NativeX64.cpp emit(rexrb(op, (Register)0, b));
op 322 nanojit/NativeX64.cpp op = op | uint64_t((r&7)<<3)<<48; // put rr[0:2] into mod/rm byte
op 323 nanojit/NativeX64.cpp op = rexrb(op, r, (Register)0); // put rr[3] into rex byte
op 324 nanojit/NativeX64.cpp emit(op);
op 333 nanojit/NativeX64.cpp emitrr(op, r, (Register)0);
op 709 nanojit/NativeX64.cpp LOpcode op = ins->opcode();
op 711 nanojit/NativeX64.cpp if (op == LIR_mul) {
op 1242 nanojit/NativeX64.cpp LOpcode op = ins->opcode();
op 1245 nanojit/NativeX64.cpp if (op == LIR_feq) {
op 1254 nanojit/NativeX64.cpp if (op == LIR_flt) {
op 1255 nanojit/NativeX64.cpp op = LIR_fgt;
op 1257 nanojit/NativeX64.cpp } else if (op == LIR_fle) {
op 1258 nanojit/NativeX64.cpp op = LIR_fge;
op 1263 nanojit/NativeX64.cpp if (op == LIR_fgt)
op 1311 nanojit/NativeX64.cpp LOpcode op = ins->opcode();
op 1316 nanojit/NativeX64.cpp switch (op) {
op 1418 nanojit/NativeX64.cpp LOpcode op = ins->opcode();
op 1419 nanojit/NativeX64.cpp switch(op) {
op 1458 nanojit/NativeX64.cpp if (op == LIR_st32f || value->isFloat() || value->isop(LIR_float) || value->isop(LIR_fmod)) {
op 1468 nanojit/NativeX64.cpp switch (op) {
op 1514 nanojit/NativeX64.cpp (op == LIR_stb) ?
op 1522 nanojit/NativeX64.cpp switch (op) {
op 359 nanojit/NativeX64.h void emit(uint64_t op);\
op 360 nanojit/NativeX64.h void emit8(uint64_t op, int64_t val);\
op 361 nanojit/NativeX64.h void emit_target8(size_t underrun, uint64_t op, NIns* target);\
op 362 nanojit/NativeX64.h void emit_target32(size_t underrun, uint64_t op, NIns* target);\
op 363 nanojit/NativeX64.h void emitrr(uint64_t op, Register r, Register b);\
op 364 nanojit/NativeX64.h void emitrxb(uint64_t op, Register r, Register x, Register b);\
op 365 nanojit/NativeX64.h void emitxb(uint64_t op, Register x, Register b) { emitrxb(op, (Register)0, x, b); }\
op 366 nanojit/NativeX64.h void emitrr8(uint64_t op, Register r, Register b);\
op 367 nanojit/NativeX64.h void emitr(uint64_t op, Register b) { emitrr(op, (Register)0, b); }\
op 368 nanojit/NativeX64.h void emitr8(uint64_t op, Register b) { emitrr8(op, (Register)0, b); }\
op 369 nanojit/NativeX64.h void emitprr(uint64_t op, Register r, Register b);\
op 370 nanojit/NativeX64.h void emitrm8(uint64_t op, Register r, int32_t d, Register b);\
op 371 nanojit/NativeX64.h void emitrm(uint64_t op, Register r, int32_t d, Register b);\
op 372 nanojit/NativeX64.h void emitrm_wide(uint64_t op, Register r, int32_t d, Register b);\
op 373 nanojit/NativeX64.h uint64_t emit_disp32(uint64_t op, int32_t d);\
op 374 nanojit/NativeX64.h void emitprm(uint64_t op, Register r, int32_t d, Register b);\
op 375 nanojit/NativeX64.h void emitrr_imm(uint64_t op, Register r, Register b, int32_t imm);\
op 376 nanojit/NativeX64.h void emitr_imm64(uint64_t op, Register r, uint64_t imm);\
op 377 nanojit/NativeX64.h void emitrxb_imm(uint64_t op, Register r, Register x, Register b, int32_t imm);\
op 378 nanojit/NativeX64.h void emitr_imm(uint64_t op, Register r, int32_t imm) { emitrr_imm(op, (Register)0, r, imm); }\
op 379 nanojit/NativeX64.h void emitr_imm8(uint64_t op, Register b, int32_t imm8);\
op 380 nanojit/NativeX64.h void emitxm_abs(uint64_t op, Register r, int32_t addr32);\
op 381 nanojit/NativeX64.h void emitxm_rel(uint64_t op, Register r, NIns* addr64);\
op 358 nanojit/Nativei386.cpp uint32_t op = i->opcode();
op 360 nanojit/Nativei386.cpp if (op == LIR_icall) {
op 363 nanojit/Nativei386.cpp else if (op == LIR_fcall) {
op 366 nanojit/Nativei386.cpp else if (op == LIR_param) {
op 376 nanojit/Nativei386.cpp else if (op == LIR_callh || (op == LIR_rsh && i->oprnd1()->opcode()==LIR_callh)) {
op 481 nanojit/Nativei386.cpp switch(op) {
op 499 nanojit/Nativei386.cpp const RegisterMask SrcRegs = (op == LIR_stb) ?
op 517 nanojit/Nativei386.cpp switch(op) {
op 644 nanojit/Nativei386.cpp if (op == LIR_st32f)
op 675 nanojit/Nativei386.cpp NanoAssertMsg(op == LIR_stqi, "asm_store64 should never receive this LIR opcode");
op 945 nanojit/Nativei386.cpp LOpcode op = ins->opcode();
op 949 nanojit/Nativei386.cpp switch (op) {
op 967 nanojit/Nativei386.cpp LOpcode op = ins->opcode();
op 970 nanojit/Nativei386.cpp if (op == LIR_mod) {
op 981 nanojit/Nativei386.cpp switch (op) {
op 1035 nanojit/Nativei386.cpp switch (op) {
op 1075 nanojit/Nativei386.cpp switch (op) {
op 1146 nanojit/Nativei386.cpp LOpcode op = ins->opcode();
op 1156 nanojit/Nativei386.cpp if (op == LIR_not)
op 1167 nanojit/Nativei386.cpp LOpcode op = ins->opcode();
op 1175 nanojit/Nativei386.cpp switch(op) {
op 1231 nanojit/Nativei386.cpp switch(op) {
op 1258 nanojit/Nativei386.cpp Register ra = getBaseReg(op, base, d, GpRegs);
op 1259 nanojit/Nativei386.cpp switch(op) {
op 1288 nanojit/Nativei386.cpp LOpcode op = ins->opcode();
op 1294 nanojit/Nativei386.cpp NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
op 1301 nanojit/Nativei386.cpp if (op == LIR_cmov) {
op 1317 nanojit/Nativei386.cpp } else if (op == LIR_qcmov) {
op 1653 nanojit/Nativei386.cpp LOpcode op = ins->opcode();
op 1685 nanojit/Nativei386.cpp if (op == LIR_fadd)
op 1687 nanojit/Nativei386.cpp else if (op == LIR_fsub)
op 1689 nanojit/Nativei386.cpp else if (op == LIR_fmul)
op 1717 nanojit/Nativei386.cpp if (op == LIR_fadd)
op 1719 nanojit/Nativei386.cpp else if (op == LIR_fsub)
op 1721 nanojit/Nativei386.cpp else if (op == LIR_fmul)
op 1723 nanojit/Nativei386.cpp else if (op == LIR_fdiv)
op 481 other-licenses/zlib/infback.c if (this.op && (this.op & 0xf0) == 0) {
op 485 other-licenses/zlib/infback.c (BITS(last.bits + last.op) >> last.bits)];
op 495 other-licenses/zlib/infback.c if (this.op == 0) {
op 507 other-licenses/zlib/infback.c if (this.op & 32) {
op 514 other-licenses/zlib/infback.c if (this.op & 64) {
op 521 other-licenses/zlib/infback.c state->extra = (unsigned)(this.op) & 15;
op 535 other-licenses/zlib/infback.c if ((this.op & 0xf0) == 0) {
op 539 other-licenses/zlib/infback.c (BITS(last.bits + last.op) >> last.bits)];
op 546 other-licenses/zlib/infback.c if (this.op & 64) {
op 554 other-licenses/zlib/infback.c state->extra = (unsigned)(this.op) & 15;
op 91 other-licenses/zlib/inffast.c unsigned op; /* code bits, operation, extra bits, or */
op 129 other-licenses/zlib/inffast.c op = (unsigned)(this.bits);
op 130 other-licenses/zlib/inffast.c hold >>= op;
op 131 other-licenses/zlib/inffast.c bits -= op;
op 132 other-licenses/zlib/inffast.c op = (unsigned)(this.op);
op 133 other-licenses/zlib/inffast.c if (op == 0) { /* literal */
op 139 other-licenses/zlib/inffast.c else if (op & 16) { /* length base */
op 141 other-licenses/zlib/inffast.c op &= 15; /* number of extra bits */
op 142 other-licenses/zlib/inffast.c if (op) {
op 143 other-licenses/zlib/inffast.c if (bits < op) {
op 147 other-licenses/zlib/inffast.c len += (unsigned)hold & ((1U << op) - 1);
op 148 other-licenses/zlib/inffast.c hold >>= op;
op 149 other-licenses/zlib/inffast.c bits -= op;
op 160 other-licenses/zlib/inffast.c op = (unsigned)(this.bits);
op 161 other-licenses/zlib/inffast.c hold >>= op;
op 162 other-licenses/zlib/inffast.c bits -= op;
op 163 other-licenses/zlib/inffast.c op = (unsigned)(this.op);
op 164 other-licenses/zlib/inffast.c if (op & 16) { /* distance base */
op 166 other-licenses/zlib/inffast.c op &= 15; /* number of extra bits */
op 167 other-licenses/zlib/inffast.c if (bits < op) {
op 170 other-licenses/zlib/inffast.c if (bits < op) {
op 175 other-licenses/zlib/inffast.c dist += (unsigned)hold & ((1U << op) - 1);
op 183 other-licenses/zlib/inffast.c hold >>= op;
op 184 other-licenses/zlib/inffast.c bits -= op;
op 186 other-licenses/zlib/inffast.c op = (unsigned)(out - beg); /* max distance in output */
op 187 other-licenses/zlib/inffast.c if (dist > op) { /* see if copy from window */
op 188 other-licenses/zlib/inffast.c op = dist - op; /* distance back in window */
op 189 other-licenses/zlib/inffast.c if (op > whave) {
op 196 other-licenses/zlib/inffast.c from += wsize - op;
op 197 other-licenses/zlib/inffast.c if (op < len) { /* some from window */
op 198 other-licenses/zlib/inffast.c len -= op;
op 201 other-licenses/zlib/inffast.c } while (--op);
op 205 other-licenses/zlib/inffast.c else if (write < op) { /* wrap around window */
op 206 other-licenses/zlib/inffast.c from += wsize + write - op;
op 207 other-licenses/zlib/inffast.c op -= write;
op 208 other-licenses/zlib/inffast.c if (op < len) { /* some from end of window */
op 209 other-licenses/zlib/inffast.c len -= op;
op 212 other-licenses/zlib/inffast.c } while (--op);
op 215 other-licenses/zlib/inffast.c op = write;
op 216 other-licenses/zlib/inffast.c len -= op;
op 219 other-licenses/zlib/inffast.c } while (--op);
op 225 other-licenses/zlib/inffast.c from += write - op;
op 226 other-licenses/zlib/inffast.c if (op < len) { /* some from window */
op 227 other-licenses/zlib/inffast.c len -= op;
op 230 other-licenses/zlib/inffast.c } while (--op);
op 261 other-licenses/zlib/inffast.c else if ((op & 64) == 0) { /* 2nd level distance code */
op 262 other-licenses/zlib/inffast.c this = dcode[this.val + (hold & ((1U << op) - 1))];
op 271 other-licenses/zlib/inffast.c else if ((op & 64) == 0) { /* 2nd level length code */
op 272 other-licenses/zlib/inffast.c this = lcode[this.val + (hold & ((1U << op) - 1))];
op 275 other-licenses/zlib/inffast.c else if (op & 32) { /* end-of-block */
op 289 other-licenses/zlib/inflate.c printf("{%u,%u,%d}", state.lencode[low].op, state.lencode[low].bits,
op 300 other-licenses/zlib/inflate.c printf("{%u,%u,%d}", state.distcode[low].op, state.distcode[low].bits,
op 962 other-licenses/zlib/inflate.c if (this.op && (this.op & 0xf0) == 0) {
op 966 other-licenses/zlib/inflate.c (BITS(last.bits + last.op) >> last.bits)];
op 974 other-licenses/zlib/inflate.c if ((int)(this.op) == 0) {
op 981 other-licenses/zlib/inflate.c if (this.op & 32) {
op 986 other-licenses/zlib/inflate.c if (this.op & 64) {
op 991 other-licenses/zlib/inflate.c state->extra = (unsigned)(this.op) & 15;
op 1007 other-licenses/zlib/inflate.c if ((this.op & 0xf0) == 0) {
op 1011 other-licenses/zlib/inflate.c (BITS(last.bits + last.op) >> last.bits)];
op 1018 other-licenses/zlib/inflate.c if (this.op & 64) {
op 1024 other-licenses/zlib/inflate.c state->extra = (unsigned)(this.op) & 15;
op 118 other-licenses/zlib/inftrees.c this.op = (unsigned char)64; /* invalid code marker */
op 220 other-licenses/zlib/inftrees.c this.op = (unsigned char)0;
op 224 other-licenses/zlib/inftrees.c this.op = (unsigned char)(extra[work[sym]]);
op 228 other-licenses/zlib/inftrees.c this.op = (unsigned char)(32 + 64); /* end of block */
op 285 other-licenses/zlib/inftrees.c (*table)[low].op = (unsigned char)curr;
op 298 other-licenses/zlib/inftrees.c this.op = (unsigned char)64; /* invalid code marker */
op 25 other-licenses/zlib/inftrees.h unsigned char op; /* operation, extra bits, table bits */
op 149 pcre/pcre_compile.cpp int op;
op 1361 pcre/pcre_compile.cpp register int op = *cc;
op 1362 pcre/pcre_compile.cpp switch (op)
op 1385 pcre/pcre_compile.cpp new_item.code = cc + ((op == OP_CBRA)? 2:0);
op 4376 pcre/pcre_compile.cpp *code = verbs[i].op;
op 5812 pcre/pcre_compile.cpp register int op = *scode;
op 5816 pcre/pcre_compile.cpp if (op == OP_BRA)
op 5826 pcre/pcre_compile.cpp else if (op == OP_CBRA)
op 5838 pcre/pcre_compile.cpp else if (op == OP_ASSERT || op == OP_ONCE || op == OP_COND)
op 5849 pcre/pcre_compile.cpp else if ((op == OP_TYPESTAR || op == OP_TYPEMINSTAR ||
op 5850 pcre/pcre_compile.cpp op == OP_TYPEPOSSTAR) && (*options & PCRE_DOTALL) != 0)
op 5860 pcre/pcre_compile.cpp else if (op != OP_SOD && op != OP_SOM &&
op 5861 pcre/pcre_compile.cpp ((*options & PCRE_MULTILINE) != 0 || op != OP_CIRC))
op 5918 pcre/pcre_compile.cpp register int op = *scode;
op 5922 pcre/pcre_compile.cpp if (op == OP_BRA)
op 5932 pcre/pcre_compile.cpp else if (op == OP_CBRA)
op 5944 pcre/pcre_compile.cpp else if (op == OP_ASSERT || op == OP_ONCE || op == OP_COND)
op 5955 pcre/pcre_compile.cpp else if (op == OP_TYPESTAR || op == OP_TYPEMINSTAR || op == OP_TYPEPOSSTAR)
op 5965 pcre/pcre_compile.cpp else if (op != OP_CIRC)
op 6027 pcre/pcre_compile.cpp register int op = *scode;
op 6029 pcre/pcre_compile.cpp switch(op)
op 6039 pcre/pcre_compile.cpp inassert = (op == OP_ASSERT);
op 559 pcre/pcre_exec.cpp int op;
op 628 pcre/pcre_exec.cpp op = *ecode;
op 638 pcre/pcre_exec.cpp switch(op)
op 718 pcre/pcre_exec.cpp flags = (op == OP_SCBRA)? match_cbegroup : 0;
op 765 pcre/pcre_exec.cpp flags = (op >= OP_SBRA)? match_cbegroup : 0;
op 856 pcre/pcre_exec.cpp if (op == OP_SCOND) /* Possibly empty group */
op 1752 pcre/pcre_exec.cpp if (op == OP_NOTPROP) RRETURN(MATCH_NOMATCH);
op 1758 pcre/pcre_exec.cpp chartype == ucp_Lt) == (op == OP_NOTPROP))
op 1763 pcre/pcre_exec.cpp if ((ecode[2] != category) == (op == OP_PROP))
op 1768 pcre/pcre_exec.cpp if ((ecode[2] != chartype) == (op == OP_PROP))
op 1773 pcre/pcre_exec.cpp if ((ecode[2] != script) == (op == OP_PROP))
op 1985 pcre/pcre_exec.cpp if (op == OP_CLASS) RRETURN(MATCH_NOMATCH);
op 2027 pcre/pcre_exec.cpp if (op == OP_CLASS) RRETURN(MATCH_NOMATCH);
op 2068 pcre/pcre_exec.cpp if (op == OP_CLASS) break;
op 76 pcre/pcre_stringpiece_unittest.cc CHECK( (StringPiece((x)) op StringPiece((y)))); \
op 77 pcre/pcre_stringpiece_unittest.cc CHECK( (StringPiece((x)).compare(StringPiece((y))) op 0))
op 80 pcre/pcre_stringpiece_unittest.cc CHECK(!(StringPiece((x)) op StringPiece((y)))); \
op 81 pcre/pcre_stringpiece_unittest.cc CHECK(!(StringPiece((x)).compare(StringPiece((y))) op 0))
op 1332 pcre/pcregrep.cpp option_item *op;
op 1334 pcre/pcregrep.cpp for (op = optionlist; op->one_char != 0; op++)
op 1336 pcre/pcregrep.cpp if (op->one_char > 0) fprintf(stderr, "%c", op->one_char);
op 1353 pcre/pcregrep.cpp option_item *op;
op 1363 pcre/pcregrep.cpp for (op = optionlist; op->one_char != 0; op++)
op 1367 pcre/pcregrep.cpp if (op->one_char > 0) sprintf(s, "-%c,", op->one_char); else strcpy(s, " ");
op 1368 pcre/pcregrep.cpp printf(" %s --%s%n", s, op->long_name, &n);
op 1371 pcre/pcregrep.cpp printf("%.*s%s\n", n, " ", op->help_text);
op 1601 pcre/pcregrep.cpp option_item *op = NULL;
op 1639 pcre/pcregrep.cpp for (op = optionlist; op->one_char != 0; op++)
op 1641 pcre/pcregrep.cpp char *opbra = strchr(op->long_name, '(');
op 1642 pcre/pcregrep.cpp char *equals = strchr(op->long_name, '=');
op 1647 pcre/pcregrep.cpp if (strcmp(arg, op->long_name) == 0) break;
op 1651 pcre/pcregrep.cpp int oplen = equals - op->long_name;
op 1653 pcre/pcregrep.cpp if (oplen == arglen && strncmp(arg, op->long_name, oplen) == 0)
op 1669 pcre/pcregrep.cpp int baselen = opbra - op->long_name;
op 1670 pcre/pcregrep.cpp sprintf(buff1, "%.*s", baselen, op->long_name);
op 1672 pcre/pcregrep.cpp (int)strlen(op->long_name) - baselen - 2, opbra + 1);
op 1678 pcre/pcregrep.cpp if (op->one_char == 0)
op 1718 pcre/pcregrep.cpp for (op = optionlist; op->one_char != 0; op++)
op 1719 pcre/pcregrep.cpp { if (*s == op->one_char) break; }
op 1720 pcre/pcregrep.cpp if (op->one_char == 0)
op 1726 pcre/pcregrep.cpp if (op->type != OP_NODATA || s[1] == 0)
op 1739 pcre/pcregrep.cpp if (op->type == OP_NODATA)
op 1741 pcre/pcregrep.cpp pcre_options = handle_option(op->one_char, pcre_options);
op 1751 pcre/pcregrep.cpp (op->type == OP_OP_STRING || op->type == OP_OP_NUMBER))
op 1753 pcre/pcregrep.cpp switch (op->one_char)
op 1782 pcre/pcregrep.cpp if (op->type == OP_PATLIST)
op 1795 pcre/pcregrep.cpp else if (op->type != OP_NUMBER && op->type != OP_OP_NUMBER)
op 1797 pcre/pcregrep.cpp *((char **)op->dataptr) = option_data;
op 1807 pcre/pcregrep.cpp char *equals = strchr(op->long_name, '=');
op 1808 pcre/pcregrep.cpp int nlen = (equals == NULL)? (int)strlen(op->long_name) :
op 1809 pcre/pcregrep.cpp equals - op->long_name;
op 1811 pcre/pcregrep.cpp option_data, nlen, op->long_name);
op 1815 pcre/pcregrep.cpp option_data, op->one_char);
op 1818 pcre/pcregrep.cpp *((int *)op->dataptr) = n;
op 766 pcre/pcretest.cpp int op = 1;
op 815 pcre/pcretest.cpp while (argc > 1 && argv[op][0] == '-')
op 819 pcre/pcretest.cpp if (strcmp(argv[op], "-s") == 0 || strcmp(argv[op], "-m") == 0)
op 821 pcre/pcretest.cpp else if (strcmp(argv[op], "-q") == 0) quiet = 1;
op 822 pcre/pcretest.cpp else if (strcmp(argv[op], "-b") == 0) debug = 1;
op 823 pcre/pcretest.cpp else if (strcmp(argv[op], "-i") == 0) showinfo = 1;
op 824 pcre/pcretest.cpp else if (strcmp(argv[op], "-d") == 0) showinfo = debug = 1;
op 826 pcre/pcretest.cpp else if (strcmp(argv[op], "-dfa") == 0) all_use_dfa = 1;
op 828 pcre/pcretest.cpp else if (strcmp(argv[op], "-o") == 0 && argc > 2 &&
op 829 pcre/pcretest.cpp ((size_offsets = get_value((unsigned char *)argv[op+1], &endptr)),
op 832 pcre/pcretest.cpp op++;
op 835 pcre/pcretest.cpp else if (strcmp(argv[op], "-t") == 0 || strcmp(argv[op], "-tm") == 0)
op 837 pcre/pcretest.cpp int both = argv[op][2] == 0;
op 839 pcre/pcretest.cpp if (argc > 2 && (temp = get_value((unsigned char *)argv[op+1], &endptr),
op 843 pcre/pcretest.cpp op++;
op 849 pcre/pcretest.cpp else if (strcmp(argv[op], "-S") == 0 && argc > 2 &&
op 850 pcre/pcretest.cpp ((stack_size = get_value((unsigned char *)argv[op+1], &endptr)),
op 867 pcre/pcretest.cpp op++;
op 872 pcre/pcretest.cpp else if (strcmp(argv[op], "-p") == 0) posix = 1;
op 874 pcre/pcretest.cpp else if (strcmp(argv[op], "-C") == 0)
op 900 pcre/pcretest.cpp else if (strcmp(argv[op], "-help") == 0 ||
op 901 pcre/pcretest.cpp strcmp(argv[op], "--help") == 0)
op 908 pcre/pcretest.cpp printf("** Unknown or malformed option %s\n", argv[op]);
op 913 pcre/pcretest.cpp op++;
op 933 pcre/pcretest.cpp infile = fopen(argv[op], INPUT_MODE);
op 936 pcre/pcretest.cpp printf("** Failed to open %s\n", argv[op]);
op 944 pcre/pcretest.cpp outfile = fopen(argv[op+1], OUTPUT_MODE);
op 947 pcre/pcretest.cpp printf("** Failed to open %s\n", argv[op+1]);
op 671 utils/superwordprof.c unsigned pc, opcode, ops, op, opcodes[10];
op 797 utils/superwordprof.c op = 0;
op 798 utils/superwordprof.c while ( op < ops ) {
op 800 utils/superwordprof.c opcode = opcodes[op];
op 806 utils/superwordprof.c compute_operands(opcodes, op, &opd1, &opd2, i, operand_value, next_symbol);
op 848 utils/superwordprof.c compute_operands(opcodes, op, &opd1, &opd2, nexttracker-1, operand_value, next_symbol);
op 858 utils/superwordprof.c op += operands[opcode] + 1;
op 861 utils/superwordprof.c assert(op == ops);